The present invention is in the technical field of the communications among digital syncronous systems and is intended to simplify the acquisition of high-rate digital signals, which are exchanged between two systems working with the same clock generator or using two different clock sources which are phase locked.
It is well-known that the phase of the digital signal on receiver side cannot be foreseen, either when the period of the clock which generates the signal is less than the delay between transmitter and receiver (delay in the transmission line+buffer delay) or comparable thereto, or when such delay can be vary due to thermal changes or voltage changes in the energy source. Therefore, to sample the signal without adjusting its phase with respect to the clock is not possible.
An object of this invention is to solve this problem, by extracting data from a synchronous digital signal, which is received with an unknown and unstable phase relationship with the local clock.
In order to make easier to understand the invention, the transmission of a digital signal from a system A to a system B is considered, with reference to FIG. 1 of annexed drawings. Said systems are electronic systems, such as a couple of assembled printed boards, a couple of integrated circuits placed on the same card or a couple of units interconnected by electric cables or optic fibres, either working with the same clock generator, or with two different clock generators which are phase-locked.
The main parameters affecting the phase of the received signal S are:
a) signal delay from A to B, due to the presence of buffers BU and BI, electric lines or electro-optical transducers;
b) delay differences in the distribution of the clock signal towards A and B;
c) possible systematic phase shifts, when employing two discrete phase-locked oscillators;
d) gap between minimum and maximum delays which are introduced by possible line buffers and in general by logic gates existing on the signal path and on the path of the clock signals; and
e) fluctuations of the above referenced parameters, depending on temperature, supply voltage and ageing.
When the period of the clock signal is comparable or less than the summation of the above reported parameters a) to e), it is impossible, from a practical point of view, to foresee with which phase the system B receives the signal in respect to its clock. Accordingly, it is not possible to acquire such a signal by regularly sampling in correspondence of an edge of the clock CB, with no risk of transgressing the setup and hold boundaries required by the sampler (usually a flip-flop) with related risks of metastability and loss of information.
To solve such a problem, a lot of methods to receive and to sample digital, high rate signals in syncronous systems are well-known. The following methods may be referred to: xe2x80x94synchronising a local oscillator with the received signal, by using a phase-locked loop and using this clock to sample such a signal; exchangeing both data and clock from system A to system B, the paths being controlled; multisampling signal S at a rate higher than the double clock frequency and processing the samples; and employing delay lines having changeable length to adjust the phase of the received signal, before its sampling.
However, the above methods are often difficult to be employed and/or to be carried out, due either to the presence of analog functions (first reported method) or to difficulties in design and construction (other methods)
This invention solves easier and safer the above problem by re-aligning the received, digital signal to the clock of the receiving system and also compensating possible time depending fluctuations of the phase of said received signal: this makes it possible to sample in an absolutely safe manner, with apparent advantage with respect to the prior-art.
More precisely, the invention relates to a process to align the phase of digital signals, in order to simplify the acquisition thereof in syncronous systems, characterised in that it comprises the following steps:
to apply a pulse width distorsion to the incoming signal;
to sample in a uniform way such a distorted signal with a frequency which is twice than the clock frequency;
to process the obtained samples, in order to re-build the bits which were present on the incoming signal; and
to introduce the so obtained bits in a buffer memory, in order to re-build the original signal, now phase-aligned.
The invention refers also to a device with electronic circuitry to carry out the above process, characterised in that it comprises: a pulse width distorsion unit, a unit that analyses and samples the distorted samples, a unit which analyses the sequences and a phase-shift register.